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/* =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-==-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
/*  »Project«   Teikitu Gaming System (TgS) (∂)
    »File«      TgS (MSVC-X86) Common - Math API [Vector] [M] [U32].inl
    »Author«    Andrew Aye (EMail: mailto:andrew.aye@gmail.com, Web: http://www.andrewaye.com)
    »Version«   4.51 / »GUID« A9981407-3EC9-42AF-8B6F-8BE6DD919615                                                                                                        */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
/*  Copyright: © 2002-2017, Andrew Aye.  All Rights Reserved.
    This software is free for non-commercial use.  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
    following conditions are met:
    Redistribution of source code must retain this copyright notice, this list of conditions and the following disclaimers.
    Redistribution in binary form must reproduce this copyright notice, this list of conditions and the following disclaimers in the documentation and other materials
    provided with the distribution.
    The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission.
    The intellectual property rights of the algorithms used reside with Andrew Aye.
    You may not use this software, in whole or in part, in support of any commercial product without the express written consent of the author.
    There is no warranty or other guarantee of fitness of this software for any purpose. It is provided solely "as is".                                                   */
/* =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-==-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
#if !defined(TGS_COMMON_MATH_API_VECTOR_M_U32_INL)
#define TGS_COMMON_MATH_API_VECTOR_M_U32_INL
#pragma once


/* == Common ============================================================================================================================================================ */

/* ---- MS_SETU_U32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 MS_SETU_U32_04( CPCU_TgUINT32 puiVal )
{
    return (_mm_loadu_si128( (__m128i*)puiVal ));
}


/* ---- MS_SETA_U32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 MS_SETA_U32_04( CPCU_TgUINT32 puiVal )
{
    return (_mm_load_si128( (__m128i*)puiVal ));
}


/* ---- MS_SET1_U32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 MS_SET1_U32_04( C_TgUINT32 uiVal )
{
    return (_mm_set1_epi32( (int)uiVal ));
}


/* ---- M_SET4_U32_04 --------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_SET4_U32_04( C_TgUINT32 uiX, C_TgUINT32 uiY, C_TgUINT32 uiZ, C_TgUINT32 uiW )
{
    return (_mm_set_epi32( (int)uiW,(int)uiZ, (int)uiY, (int)uiX ));
}


/* ---- M_PERM_U32_04 --------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_PERM_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight, C_TgVEC_M_U32_04 tuvMask )
{
    __m128i                             vX = { 0 };
    TgUINT32                            uiIndex;

    for (uiIndex = 0; uiIndex < 4; ++uiIndex)
    {
        C_TgUINT08                          byMask = tuvMask.m128i_u8[uiIndex];
        C_TgUINT32                          ui0 = tvLeft.m128i_u32[byMask & 0x3];
        C_TgUINT32                          ui1 = tvRight.m128i_u32[byMask & 0x3];

        vX.m128i_u32[uiIndex] = 0 == (byMask & KTgPERM_PARAM_SELECT_BIT) ? ui0 : ui1;
    };

    return (vX);
}


/* ---- M_SEL_U32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_SEL_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight, C_TgVEC_M_U32_04 tuvMask )
{
    return (_mm_or_si128( _mm_and_si128( tvLeft, _mm_xor_si128( KTgV_FFFF.m_u32_v04.m_mData, tuvMask ) ), _mm_and_si128( tvRight, tuvMask ) ));
}


/* ---- M_AND_U32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_AND_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_and_si128( tvLeft, tvRight ));
}


/* ---- M_OR_U32_04 ----------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_OR_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_or_si128( tvLeft, tvRight ));
}


/* ---- M_XOR_U32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_XOR_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_xor_si128( tvLeft, tvRight ));
}


/* ---- M_MAX_U32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_MAX_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_max_epu32( tvLeft, tvRight ));
}


/* ---- M_MIN_U32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_MIN_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_min_epu32( tvLeft, tvRight ));
}


/* ---- M_CMP_EQ_U32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_CMP_EQ_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_cmpeq_epi32( tvLeft, tvRight ));
}


/* ---- M_CMP_NE_U32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_CMP_NE_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_xor_si128( KTgV_FFFF.m_u32_v04.m_mData, _mm_cmpeq_epi32( tvLeft, tvRight ) ));
}


/* ---- M_CMP_GE_U32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_CMP_GE_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_xor_si128( KTgV_FFFF.m_u32_v04.m_mData, M_CMP_GT_U32_04( tvRight, tvLeft ) ));
}


/* ---- M_CMP_GT_U32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_CMP_GT_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    __m128i                             vX1;

    vX1.m128i_u32[0] = tvLeft.m128i_u32[0] > tvRight.m128i_u32[0] ? 0xFFFFFFFF : 0x00000000;
    vX1.m128i_u32[1] = tvLeft.m128i_u32[1] > tvRight.m128i_u32[1] ? 0xFFFFFFFF : 0x00000000;
    vX1.m128i_u32[2] = tvLeft.m128i_u32[2] > tvRight.m128i_u32[2] ? 0xFFFFFFFF : 0x00000000;
    vX1.m128i_u32[3] = tvLeft.m128i_u32[3] > tvRight.m128i_u32[3] ? 0xFFFFFFFF : 0x00000000;

    return (vX1);
}


/* ---- M_CMP_LE_U32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_CMP_LE_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (_mm_xor_si128( KTgV_FFFF.m_u32_v04.m_mData, M_CMP_GT_U32_04( tvLeft, tvRight ) ));
}


/* ---- TgVEC_M_U32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_CMP_LT_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (M_CMP_GT_U32_04( tvRight, tvLeft ));
}


/* ---- M_ADD_S_U32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_ADD_S_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (F_ADD_S_U32_04( (P_TgVEC_U32_04)&tvLeft, (P_TgVEC_U32_04)&tvRight ).m_mData);
}


/* ---- M_ADD_M_U32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_ADD_M_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (F_ADD_M_U32_04( (P_TgVEC_U32_04)&tvLeft, (P_TgVEC_U32_04)&tvRight ).m_mData);
}


/* ---- M_SUB_S_U32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_SUB_S_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (F_SUB_S_U32_04( (P_TgVEC_U32_04)&tvLeft, (P_TgVEC_U32_04)&tvRight ).m_mData);
}


/* ---- M_SUB_M_U32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_SUB_M_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (F_SUB_M_U32_04( (P_TgVEC_U32_04)&tvLeft, (P_TgVEC_U32_04)&tvRight ).m_mData);
}


/* ---- M_AVG_U32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_U32_04 M_AVG_U32_04( C_TgVEC_M_U32_04 tvLeft, C_TgVEC_M_U32_04 tvRight )
{
    return (F_AVG_U32_04( (P_TgVEC_U32_04)&tvLeft, (P_TgVEC_U32_04)&tvRight ).m_mData);
}


/* ====================================================================================================================================================================== */
#endif