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/* =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-==-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
/*  »Project«   Teikitu Gaming System (TgS) (∂)
    »File«      TgS (MSVC-X86) Common - Math API [Vector] [M] [F32_04].inl
    »Author«    Andrew Aye (EMail: mailto:andrew.aye@gmail.com, Web: http://www.andrewaye.com)
    »Version«   4.51 / »GUID« A9981407-3EC9-42AF-8B6F-8BE6DD919615                                                                                                        */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
/*  Copyright: © 2002-2017, Andrew Aye.  All Rights Reserved.
    This software is free for non-commercial use.  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
    following conditions are met:
    Redistribution of source code must retain this copyright notice, this list of conditions and the following disclaimers.
    Redistribution in binary form must reproduce this copyright notice, this list of conditions and the following disclaimers in the documentation and other materials
    provided with the distribution.
    The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission.
    The intellectual property rights of the algorithms used reside with Andrew Aye.
    You may not use this software, in whole or in part, in support of any commercial product without the express written consent of the author.
    There is no warranty or other guarantee of fitness of this software for any purpose. It is provided solely "as is".                                                   */
/* =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-==-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
#if !defined(TGS_COMMON_MATH_API_VECTOR_M_F32_04_INL)
#define TGS_COMMON_MATH_API_VECTOR_M_F32_04_INL
#pragma once


/* == Common ============================================================================================================================================================ */

/* ---- V(MS_SET) ------------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 MS_SET_F32_04( C_TgFLOAT32 fX, C_TgFLOAT32 fY, C_TgFLOAT32 fZ, C_TgFLOAT32 fW )
{
    return (_mm_set_ps( fW, fZ, fY, fX ));
}


/* ---- V(MS_SETP) ------------------------------------------------------------------------------------------------------------------------------------------------------ */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 MS_SETP_F32_04( C_TgFLOAT32 fX, C_TgFLOAT32 fY, C_TgFLOAT32 fZ )
{
    return (MS_SET_F32_04( fX, fY, fZ, 1.0F ));
}


/* ---- V(MS_SETV) ------------------------------------------------------------------------------------------------------------------------------------------------------ */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 MS_SETV_F32_04( C_TgFLOAT32 fX, C_TgFLOAT32 fY, C_TgFLOAT32 fZ )
{
    return (MS_SET_F32_04( fX, fY, fZ, 0.0F ));
}


/* ---- V4(M_SETP) ------------------------------------------------------------------------------------------------------------------------------------------------------ */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_SETP_F32_04( C_TgVEC_M_F32_04 tvRight )
{
    return (M_OR_F32_04( KTgV_UNIT_W_F32_04.m_mData, M_AND_F32_04( tvRight, KTgV_FFF0.m_f32_v04.m_mData ) ));
}


/* ---- V4(M_SETV) ------------------------------------------------------------------------------------------------------------------------------------------------------ */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_SETV_F32_04( C_TgVEC_M_F32_04 tvRight )
{
    return (M_AND_F32_04( tvRight, KTgV_FFF0.m_f32_v04.m_mData ));
}


/* ---- V4(M_SPX) ------------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_SPX_F32_04( C_TgVEC_M_F32_04 tvLeft )
{
    return (_mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 0, 0, 0, 0 ) ));
}


/* ---- V4(M_SPY) ------------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_SPY_F32_04( C_TgVEC_M_F32_04 tvLeft )
{
    return (_mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 1, 1, 1, 1 ) ));
}


/* ---- V4(M_SPZ) ------------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_SPZ_F32_04( C_TgVEC_M_F32_04 tvLeft )
{
    return (_mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 2, 2, 2, 2 ) ));
}


/* ---- V4(M_SPW) ------------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_SPW_F32_04( C_TgVEC_M_F32_04 tvLeft )
{
    return (_mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 3, 3, 3, 3 ) ));
}


/* ---- V4(M_DOT3) ------------------------------------------------------------------------------------------------------------------------------------------------------ */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_DOT3_F32_04( C_TgVEC_M_F32_04 tvLeft, C_TgVEC_M_F32_04 tvRight )
{
    const __m128                        vX1 = _mm_mul_ps( tvLeft, tvRight );
    const __m128                        vX2 = _mm_shuffle_ps( vX1, vX1, _MM_SHUFFLE( 2, 1, 2, 1 ) );
    const __m128                        vX3 = _mm_add_ss( vX1, vX2 );
    const __m128                        vX4 = _mm_shuffle_ps( vX2, vX2, _MM_SHUFFLE( 1, 1, 1, 1 ) );
    const __m128                        vX5 = _mm_add_ss( vX3, vX4 );

    return (_mm_shuffle_ps( vX5, vX5, _MM_SHUFFLE( 0, 0, 0, 0 ) ));
}


/* ---- V4(M_CX) -------------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_CX_F32_04( C_TgVEC_M_F32_04 tvLeft, C_TgVEC_M_F32_04 tvRight )
{
    const __m128                        vX1 = _mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 3, 1, 0, 2 ) );
    const __m128                        vX2 = _mm_shuffle_ps( tvRight, tvRight, _MM_SHUFFLE( 3, 0, 2, 1 ) );
    const __m128                        vX3 = _mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 3, 0, 2, 1 ) );
    const __m128                        vX4 = _mm_shuffle_ps( tvRight, tvRight, _MM_SHUFFLE( 3, 1, 0, 2 ) );

    return (_mm_sub_ps( _mm_mul_ps( vX3, vX4 ), _mm_mul_ps( vX1, vX2 ) ));
}


/* ---- V4(M_UCX) ------------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_UCX_F32_04( C_TgVEC_M_F32_04 tvLeft, C_TgVEC_M_F32_04 tvRight )
{
    const __m128                        vX1 = _mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 3, 1, 0, 2 ) );
    const __m128                        vX2 = _mm_shuffle_ps( tvRight, tvRight, _MM_SHUFFLE( 3, 0, 2, 1 ) );
    const __m128                        vX3 = _mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 3, 0, 2, 1 ) );
    const __m128                        vX4 = _mm_shuffle_ps( tvRight, tvRight, _MM_SHUFFLE( 3, 1, 0, 2 ) );
    const __m128                        vF0 = _mm_sub_ps( _mm_mul_ps( vX3, vX4 ), _mm_mul_ps( vX1, vX2 ) );

    return (M_NORM_F32_04( (vF0) ));
}


/* ---- V4(M_UCX_LEN) --------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_UCX_LEN_F32_04( PCU_TgVEC_M_F32_04 ptvRet_Length, C_TgVEC_M_F32_04 tvLeft, C_TgVEC_M_F32_04 tvRight )
{
    const __m128                        vX1 = _mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 3, 1, 0, 2 ) );
    const __m128                        vX2 = _mm_shuffle_ps( tvRight, tvRight, _MM_SHUFFLE( 3, 0, 2, 1 ) );
    const __m128                        vX3 = _mm_shuffle_ps( tvLeft, tvLeft, _MM_SHUFFLE( 3, 0, 2, 1 ) );
    const __m128                        vX4 = _mm_shuffle_ps( tvRight, tvRight, _MM_SHUFFLE( 3, 1, 0, 2 ) );
    const __m128                        vF0 = _mm_sub_ps( _mm_mul_ps( vX3, vX4 ), _mm_mul_ps( vX1, vX2 ) );

    return (M_NORM_LEN_F32_04( ptvRet_Length, (vF0) ));
}


/* ---- V4(M_PRX3) ------------------------------------------------------------------------------------------------------------------------------------------------------ */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgBOOL M_PRX3_F32_04( C_TgVEC_M_F32_04 v0, C_TgVEC_M_F32_04 v1 )
{
    return F_PRX3_F32_04( (CP_TgVEC_F32_04)&v0, (CP_TgVEC_F32_04)&v1 );
}


/* ---- V4(M_PRX4) ------------------------------------------------------------------------------------------------------------------------------------------------------ */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgBOOL M_PRX4_F32_04( C_TgVEC_M_F32_04 v0, C_TgVEC_M_F32_04 v1 )
{
    return F_PRX4_F32_04( (CP_TgVEC_F32_04)&v0, (CP_TgVEC_F32_04)&v1 );
}


/* ---- V4(M_QT_INV) ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_QT_INV_F32_04( C_TgVEC_M_F32_04 qR1 )
{
    const __m128                        vResult = F_QT_INV_F32_04( (CP_TgVEC_F32_04)&qR1 ).m_mData;
    return vResult;
}


/* ---- V4(M_QT_MUL) ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_QT_MUL_F32_04( C_TgVEC_M_F32_04 b, C_TgVEC_M_F32_04 c )
{
    return (F_QT_MUL_F32_04( (CP_TgVEC_F32_04)&b, (CP_TgVEC_F32_04)&c ).m_mData);
}


/* ---- V4(M_QT_SLERP) -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_QT_SLERP_F32_04( C_TgVEC_M_F32_04 b, C_TgVEC_M_F32_04 c, C_TgVEC_M_F32_04 d )
{
    return (F_QT_SLERP_F32_04( *(CP_TgFLOAT32)&b, (CP_TgVEC_F32_04)&c, (CP_TgVEC_F32_04)&d ).m_mData);
}


/* ---- V4(M_QT_VECTOR_TO_VECTOR) --------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_QT_VECTOR_TO_VECTOR_F32_04( C_TgVEC_M_F32_04 b, C_TgVEC_M_F32_04 c )
{
    return (F_QT_VECTOR_TO_VECTOR_F32_04( (CP_TgVEC_F32_04)&b, (CP_TgVEC_F32_04)&c ).m_mData);
}


/* ---- V4(M_QT_TX) ----------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_QT_TX_F32_04( C_TgVEC_M_F32_04 qR1, C_TgVEC_M_F32_04 qR2 )
{
    const __m128                        vResult = F_QT_TX_F32_04( (CP_TgVEC_F32_04)&qR1, (CP_TgVEC_F32_04)&qR2 ).m_mData;
    return vResult;
}


/* ---- V4(M_QT_INV_TX) ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_F32_04 M_QT_INV_TX_F32_04( C_TgVEC_M_F32_04 qR1, C_TgVEC_M_F32_04 qR2 )
{
    const __m128                        vResult = F_QT_INV_TX_F32_04( (CP_TgVEC_F32_04)&qR1, (CP_TgVEC_F32_04)&qR2 ).m_mData;
    return vResult;
}


/* ====================================================================================================================================================================== */
#endif