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/* =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-==-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
/*  »Project«   Teikitu Gaming System (TgS) (∂)
    »File«      TgS (CLANG-X86) Common - Math API [Vector] [M] [S32].inl
    »Author«    Andrew Aye (EMail: mailto:andrew.aye@gmail.com, Web: http://www.andrewaye.com)
    »Version«   4.51 / »GUID« A9981407-3EC9-42AF-8B6F-8BE6DD919615                                                                                                        */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
/*  Copyright: © 2002-2017, Andrew Aye.  All Rights Reserved.
    This software is free for non-commercial use.  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
    following conditions are met:
    Redistribution of source code must retain this copyright notice, this list of conditions and the following disclaimers.
    Redistribution in binary form must reproduce this copyright notice, this list of conditions and the following disclaimers in the documentation and other materials
    provided with the distribution.
    The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission.
    The intellectual property rights of the algorithms used reside with Andrew Aye.
    You may not use this software, in whole or in part, in support of any commercial product without the express written consent of the author.
    There is no warranty or other guarantee of fitness of this software for any purpose. It is provided solely "as is".                                                   */
/* =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-==-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= */
#if !defined(TGS_COMMON_MATH_API_VECTOR_M_S32_INL)
#define TGS_COMMON_MATH_API_VECTOR_M_S32_INL
#pragma once


/* == Common ============================================================================================================================================================ */

/* ---- MS_SETU_S32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 MS_SETU_S32_04( CPCU_TgSINT32 puiVal )
{
    return ((TgVEC_M_S32_04)_mm_loadu_si128( (const __m128i*)puiVal ));
}


/* ---- MS_SETA_S32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 MS_SETA_S32_04( CPCU_TgSINT32 puiVal )
{
    return ((TgVEC_M_S32_04)_mm_load_si128( (const __m128i*)puiVal ));
}


/* ---- MS_SET1_S32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 MS_SET1_S32_04( C_TgSINT32 iVal )
{
    return ((TgVEC_M_S32_04)_mm_set1_epi32( iVal ));
}


/* ---- M_SET4_S32_04 --------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_SET4_S32_04( C_TgSINT32 fX, C_TgSINT32 fY, C_TgSINT32 fZ, C_TgSINT32 fW )
{
    return ((TgVEC_M_S32_04)_mm_set_epi32( fW, fZ, fY, fX ));
}


/* ---- M_PERM_S32_04 --------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_PERM_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight, C_TgVEC_M_S32_04 tuvMask )
{
    __m128i                             vX = { 0 };
    TgUINT32                            uiIndex;

    for (uiIndex = 0; uiIndex < 4; ++uiIndex)
    {
        C_TgSINT32                          byMask = tuvMask[uiIndex];
        C_TgSINT32                          i0 = tvLeft[byMask & 0x3];
        C_TgSINT32                          i1 = tvRight[byMask & 0x3];

        vX[uiIndex] = 0 == (byMask & KTgPERM_PARAM_SELECT_BIT) ? i0 : i1;
    };

    return ((TgVEC_M_S32_04)vX);
}


/* ---- M_SEL_S32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_SEL_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight, C_TgVEC_M_S32_04 tuvMask )
{
    return ((TgVEC_M_S32_04)_mm_or_si128( _mm_and_si128( (const __m128i)tvLeft, _mm_xor_si128( (const __m128i)KTgV_FFFF.m_i32_v04.m_mData, (const __m128i)tuvMask ) ), _mm_and_si128( (const __m128i)tvRight, (const __m128i)tuvMask ) ));
}


/* ---- M_AND_S32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_AND_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_and_si128( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_OR_S32_04 ----------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_OR_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_or_si128( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_XOR_S32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_XOR_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_xor_si128( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_MAX_S32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_MAX_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_max_epi32( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_MIN_S32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_MIN_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_min_epi32( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_CMP_EQ_S32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_CMP_EQ_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_cmpeq_epi32( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_CMP_NE_S32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_CMP_NE_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_xor_si128( (const __m128i)KTgV_FFFF.m_i32_v04.m_mData, _mm_cmpeq_epi32( (const __m128i)tvLeft, (const __m128i)tvRight ) ));
}


/* ---- M_CMP_GE_S32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_CMP_GE_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_xor_si128( (const __m128i)KTgV_FFFF.m_i32_v04.m_mData, _mm_cmpgt_epi32( (const __m128i)tvRight, (const __m128i)tvLeft ) ));
}


/* ---- M_CMP_GT_S32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_CMP_GT_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_cmpgt_epi32( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_CMP_LE_S32_04 ------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_CMP_LE_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_xor_si128( (const __m128i)KTgV_FFFF.m_i32_v04.m_mData, _mm_cmpgt_epi32( (const __m128i)tvLeft, (const __m128i)tvRight ) ));
}


/* ---- TgVEC_M_S32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_CMP_LT_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_cmpgt_epi32( (const __m128i)tvRight, (const __m128i)tvLeft ));
}


/* ---- M_ADD_S_S32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_ADD_S_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return (F_ADD_S_S32_04( (CP_TgVEC_S32_04)&tvLeft, (CP_TgVEC_S32_04)&tvRight ).m_mData);
}


/* ---- M_ADD_M_S32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_ADD_M_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_add_epi32( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_SUB_S_S32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_SUB_S_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return (F_SUB_S_S32_04( (CP_TgVEC_S32_04)&tvLeft, (CP_TgVEC_S32_04)&tvRight ).m_mData);
}


/* ---- M_SUB_M_S32_04 -------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_SUB_M_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return ((TgVEC_M_S32_04)_mm_sub_epi32( (const __m128i)tvLeft, (const __m128i)tvRight ));
}


/* ---- M_AVG_S32_04 ---------------------------------------------------------------------------------------------------------------------------------------------------- */
/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- */
TgINLINE TgVEC_M_S32_04 M_AVG_S32_04( C_TgVEC_M_S32_04 tvLeft, C_TgVEC_M_S32_04 tvRight )
{
    return (F_AVG_S32_04( (CP_TgVEC_S32_04)&tvLeft, (CP_TgVEC_S32_04)&tvRight ).m_mData);
}


/* ====================================================================================================================================================================== */
#endif